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Altera_Forum
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11 years ago

Cyclone V PLL Lock & Startup Time

I have a board with Cyclone VE, the A7. I'm in the process of bringing up the board. This is basically a VHDL Top Level file that instantiates the PLL and a heartbeat counter to toggle some LED's. You know the story, if you can't make a heartbeat, then you have problems. Basically, on 50% of my boards that I have tested, the pll does not lock. I am trying to sort out whether this is a hardware problem or some specific setting that I'm ignoring in the PLL Megawizard setup for Cyclone V PLL.

I've noticed that the Quartus megafunction is different for the PLL on Cyclone V versus Cyclone IV. It uses the Qsys style megafunction and has the fractional PLL aspects. All this is fine, as I can generate the Megawizard and I have set it up to take in a 50 MHz clock and generate a 1, 10, 50, 100, and 200 MHz clock(s). The locked signals are present as well as the rst signal for the pll.

I am wondering if anyone else has had issues with Cyclone V PLL's generated from the Megawizard. Thanks. James

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Jamess,

    I'd check that you have good enough filtering on the PLL supplies and a good input clock first.

    I've been experimenting on an RF board with a C IV fed with a 20MHz clock into the PLL. The RF guy said the 20MHz clock was generating a lot of spurious

    noise so we tried slugging it a bit, it didn't take a lot before the PLL wouldn't lock.

    Nial.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Nial

    Yes. The cycle to cycle jitter spec on Cyclone V is 750 ps for an input clock of less than 100 MHz, which is my case. I am going with higher quality crystals initially.

    However, to add to the confusion, the new PLL megawizard generates verilog that is wrapped by VHDL. Since I'm using VHDL, that is all good. However, since I am using direct instantiation of the module, Quartus didn't like this in compile time. So I manually had to take the .vhd and .v files from the Megawizard and put them in the main path of the Quartus project for direct instantiation to work. i.e. the following below in terms of "direct instantiation" 

    	U1a: entity work.PLL_200(syn) 
		port map(
		inclk0   	        => CLK,
		c0	 		=> MCLK_1,
		c1	 		=> MCLK_50,
		c2    	                => MCLK,
		c3                     => MCLK_200,
		c4                     => MCLK_25,
		locked	        => pll_locked 
	);