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Honored Contributor
Honored ContributorCyclone V PLL Lock & Startup Time
I have a board with Cyclone VE, the A7. I'm in the process of bringing up the board. This is basically a VHDL Top Level file that instantiates the PLL and a heartbeat counter to toggle some LED's. Yo...
Altera_ForumHonored Contributor
Honored ContributorJamess,
I'd check that you have good enough filtering on the PLL supplies and a good input clock first. I've been experimenting on an RF board with a C IV fed with a 20MHz clock into the PLL. The RF guy said the 20MHz clock was generating a lot of spurious noise so we tried slugging it a bit, it didn't take a lot before the PLL wouldn't lock. Nial.
