Cyclone V PLL Lock & Startup Time

Nial

Yes. The cycle to cycle jitter spec on Cyclone V is 750 ps for an input clock of less than 100 MHz, which is my case. I am going with higher quality crystals initially.

However, to add to the confusion, the new PLL megawizard generates verilog that is wrapped by VHDL. Since I'm using VHDL, that is all good. However, since I am using direct instantiation of the module, Quartus didn't like this in compile time. So I manually had to take the .vhd and .v files from the Megawizard and put them in the main path of the Quartus project for direct instantiation to work. i.e. the following below in terms of "direct instantiation"

	U1a: entity work.PLL_200(syn) 
		port map(
		inclk0   	        => CLK,
		c0	 		=> MCLK_1,
		c1	 		=> MCLK_50,
		c2    	                => MCLK,
		c3                     => MCLK_200,
		c4                     => MCLK_25,
		locked	        => pll_locked 
	);