Cyclone V PLL Clock Switching

Can anyone clarify the behavior of the Cyclone V PLL clock switching logic.

We have two potential clock sources (both 10Mhz) (one that may not be present) and would like to switch to the clock that may or may not be present.

With a Cyclone III this worked perfectly, we jsut conencted into the pll clock switch and everything worked, with a bit of logic to ensure that the prefered clock was selected if present.

Issue 156380 on altera knowledge base states that the Cyclone V pll clock switch needs both clocks. And test so far indicates this is the case. Found this out after build a new board. Even worse reading thru the manual finds:

the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs. When they are asserted, the clock sense block detects that the corresponding clock input has stopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1 is greater than 20%.

and:

Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate the manual

clock switchover event. Failing to meet this requirement causes the clock switchover to not function

properly.

As I do have other clocks available that are always present I trying to wrap some logic around the block to detect and trigger a change. But it looks like the status lines are potential useless and to switch manually you need both clocks present anyways. All in all the clock switching seems worthless.

Has anyone had any luck getting clock switch to work reliably with Cycone V's when one clock isn't there?

Regards

Phil