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Altera_Forum
Honored Contributor
Honored ContributorCyclone V PLL Clock Switching
Can anyone clarify the behavior of the Cyclone V PLL clock switching logic. We have two potential clock sources (both 10Mhz) (one that may not be present) and would like to switch to the clock ...
niosIIuser
New Contributor
New ContributorDear Phil,
When googling for this issue I found your quite old post. I assume that you found a solution for your design. Here is mine – in case someone else is looking to get a hint.
I implemented a separate clock detection VHDL module which outputs a clock fault signal in case the to be checked clocked does not clock correctly. This module is complete independent and works with a separate clock (in my case the one which comes directly from the external oscillator). By doing so is possible to check also clocks which do not clock anymore.
The clock fault from the module above feeds another logic which triggers extswitch in case clock fault is negative and the activclk is the other one.
Good luck,
Andy
