New ContributorCyclone V PCIe Reconfigure Busy Signal
Hello,
I am working on a Cyclone V GT PCIe endpoint system in Platform Designer (Quartus version 24.1 Standard Edition). The system is based on the ep_g2x4 reference design (using the Avalon-MM Cyclone V Hard IP for PCI Express).
I am trying to figure out what needs to be done with the "reconfig_busy" input to the hard IP. It seems the reconfiguration busy signal is already used between the transceiver reconfiguration IP and the PCIe reconfiguration driver IP.
There are two mentions that I see of this signal in the Cyclone V Avalon-MM Interface for PCI Express manual (document 683494).
The first mention is in the transceiver control signals section.
busy_xcvr_reconfig - Input - When asserted, indicates that the a reconfiguration operation is in progress.
In the Revision History, it mentions that the reconfig_busy signal connection between the PCIe IP core and the reconfig controller was removed.
Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver.
In the Platform Designer reference design, this signal is exported, which doesn't help.
This info doesn't help me determine how this signal needs to be driven. Since this is handled by the transceiver reconfiguration IP and the PCIe reconfiguration driver IP, is it sufficient to drive the reconfig_busy input to the PCIe IP to '0'? Thanks in advance.
Hi,
For those reconfig pins on the PCIe IP, you can wire all input signals(except clk and rst) to 0 if you don't need them.
Connect clk to a slow clock and deassert rst.
Regards,
Rong
