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jc_ddc's avatar
jc_ddc
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8 days ago
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Cyclone V PCIe Reconfigure Busy Signal

Hello, I am working on a Cyclone V GT PCIe endpoint system in Platform Designer (Quartus version 24.1 Standard Edition). The system is based on the ep_g2x4 reference design (using the Avalon-MM Cycl...
Programmable Logic Device
  • RongY_altera's avatar
    RongY_altera
    3 days ago

    Hi,

    For those reconfig pins on the PCIe IP, you can wire all input signals(except clk and rst) to 0 if you don't need them.

    Connect clk to a slow clock and deassert rst.

     

    Regards,

    Rong

RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
3 days ago

Hi,

For those reconfig pins on the PCIe IP, you can wire all input signals(except clk and rst) to 0 if you don't need them.

Connect clk to a slow clock and deassert rst.

 

Regards,

Rong

jc_ddc's avatar
jc_ddc
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3 days ago

Hi Rong,

Great, thank you!