Forum Discussion

John_C's avatar
John_C
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Cyclone V HMC IBIS Model

I cannot find the IBIS model for the Cyclone V HMC (Hard memory controller). I tried looking here https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-...
Board Debug
Configuration
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    1 year ago

    Hi John_C,


    I think you should follow the IO standard that the IP is currently using to connect the memory component.

    For example DDR3, the IO standard is SSTL-15. You can use SSTL15_<io>_<feature> or similar IBIS model.



    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi John_C,


I think you should follow the IO standard that the IP is currently using to connect the memory component.

For example DDR3, the IO standard is SSTL-15. You can use SSTL15_<io>_<feature> or similar IBIS model.



Regards,

Adzim


John_C's avatar
John_C
Icon for New Contributor rankNew Contributor
1 year ago

This is what I had ended up using. Thank you.