WaveSolver
New Contributor
6 years agoCyclone V GX Transceiver - vanilla LVDS RX
Hi,
This is my first post on the Intel FPGA community! I believe this can be done with the Cyclone V GX transceiver, but can someone please confirm:
- Receive one LVDS data channel with a separate LVDS clock signal, data rate of 1.04 Gbps, serialization factor of 16 (clock rate of 65 MHz).
- Assuming this is possible, is there an example design such an application? This transceiver is surprisingly complex.
I've spent most of the day learning about the Cyclone V GX transceiver and searching for examples and answers to my specific question but found nothing useful. Any help is appreciated!