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WaveSolver's avatar
WaveSolver
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5 years ago

Cyclone V GX Transceiver - vanilla LVDS RX

Hi, This is my first post on the Intel FPGA community! I believe this can be done with the Cyclone V GX transceiver, but can someone please confirm: Receive one LVDS data channel with a separat...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, you would like to configure the CV transceiver to run at 1.04Gbps with SERDES factor of 16. For your information, you can use the Native PHY IP to configure the CV transceiver. As I checked using the Native PHY IP, there should be no issue to achieve your target configuration.


For your information, there seems to be no specific example design per your target configuration. I have sent you a simulation example previous from wiki to your email for reference. This example is showing a CV Native PHY running with bitslip mode. You refer to the example on the modules required and interconnection between them. Hopefully it helps a quicker start.


  • WaveSolver's avatar
    WaveSolver
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thanks for the reply! I see that I posted my question to the wrong category <facepalm>.

    Can you please resend the example project? I received a very short email with no attachments.

  • WaveSolver's avatar
    WaveSolver
    Icon for New Contributor rankNew Contributor
    5 years ago

    Can you please resend the example transceiver RX project? Your first email did not have an attachment. Thanks!

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Sorry as I might have overlooked the email notification from your previous post. I have tried posting the design here to see if it can get through.