Honored ContributorCyclone V GX PLL not locking
I have a cyclone V GX on a custom board on which the PLLs do not consistently lock on to the reference clock. The board is based on the terasic Cyclone V GX development board and has the same SiLabs 5338 external PLL generating 125Mhz and 50Mhz along with a 50Mhz oscillator fed into the FPGA through a clock buffer. This provides 4 50Mhz reference clocks and 1 125Mhz reference clock. When I try to generate 2 100Mhz clocks from 2 separate PLLs fed by a 50Mhz and the 125Mhz one PLL will lock and the other will not. When I load the same design into 2 different boards I get inconsistent results, on one board the 125Mhz derived PLL will lock and the 50Mhz will not. While on the other board the 50Mhz derived PLL will lock and the 125Mhz will not. If I change which 50Mhz oscillator is fed to the 50Mhz PLL the results also change with a working 125Mhz sometimes failing to lock and the 50Mhz becoming functional. I have examined the clocks with an oscilloscope and the signal is clean and there is little jitter. I have also looked that the FPLL power supply and there is only 10mVpp-20mVpp ripple. The compile to compile variation seems to be due to which physical PLL quartus assigns, but I can't find anything which would cause the board to board variation. Any suggestions for how to debug or what the issue might be would be very appreciated.
