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Honored Contributor
Honored ContributorCyclone V GX PLL not locking
I have a cyclone V GX on a custom board on which the PLLs do not consistently lock on to the reference clock. The board is based on the terasic Cyclone V GX development board and has the same SiLabs ...
Altera_ForumHonored Contributor
Honored ContributorFurther debugging has shown that on one board of the 6 physical PLL blocks shown in the chip planner. When 6 PLLs are instantiated from the same clock source the same 2 physical PLLs will lock on and oscillate no matter what clock source is used. Of the remaining 4, 2 will oscillate but not assert the locked signal, and 2 will be stuck high or low with no lock signal.
FRACTIONALPLL_X0_Y54_N0 locks and oscillates FRACTIONALPLL_X0_Y30_N0 oscillates FRACTIONALPLL_X0_Y14_N0 stuck high or low FRACTIONALPLL_X0_Y1_N0 locks and oscillates FRACTIONALPLL_X68_Y1_N0 oscillates FRACTIONALPLL_X68_Y54_N0 stuck high or low
