Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThanks for the reply, I wasn't aware that could be an issue. In the end I only need one PLL to function for the design, I just tested all of them at once to see which ones would lock and which wouldn't. I did a series or tests where I only instantiated one PLL and assigned it to each physical PLL in turn. The results matched the 6PLL test with X0_Y54 and X0_Y1 working properly and the rest not. Unfortunately when tested across 3 boards there isn't one PLL with locks on all three, that would at least allow things to push forward.