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Altera_Forum
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9 years ago

Cyclone V GX PLL not locking

I have a cyclone V GX on a custom board on which the PLLs do not consistently lock on to the reference clock. The board is based on the terasic Cyclone V GX development board and has the same SiLabs ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Multiple PLLs running at or near the same frequency can "talk" to each other and cause problems. This may be a situation where you have to manually change PLL settings to vary the VCO frequencies between the PLLs. Here's is one mention about this issue from Altera:

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd03282014_193.html

This does not apply to Cyclone V, but I think the principles always apply. You may have to rethink you clocking architecture to get around this. I would open a service request with Altera and see if they have any restrictions or guidelines that you're not aware of.