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Altera_Forum
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9 years ago

Cyclone V GX PLL not locking

I have a cyclone V GX on a custom board on which the PLLs do not consistently lock on to the reference clock. The board is based on the terasic Cyclone V GX development board and has the same SiLabs ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

eventually found my problem, I went through the pin config document again and realized we accidentally left the RREF_TL pin unconnected. The document states it needs to be connected through a 2K 1% resistor to ground, and the Terasic reference design includes it. Luckily it is on an edge ball so I was able to rework in a piece of magnet wire and connect the resistor. Once I did all of the PLLs in my test case started running and locking properly.