Cyclone V FPGA configuration

Hello,

My platform configuration :

• Cyclone V SoC FPGA
• ECPQ memory connected to FPGA through AS
• MSEL pins set to use AS configuration scheme

I store a FPGA configuration in EPCQ memory. While booting, FPGA is configured through AS link.

The question is :

Is it possible to reconfigure FPGA (with a new configuration and without changing MSEL pins setting) through HPS while functionning ?

In Cyclone V Device Handbook Volume 1, I found out that MSEL pins are sampled during Reste state execution :

And in Cyclone V HPS Reference Manual, I found this :

Does it mean that FPGA Manager always starts by executing Reset state when configuring FPGA ? Regardless of the fact that it is processing full reconfiguration or partial reconfiguration ? Am I missing/misunderstanding something in the documentation ?

Thanks for the help