Cyclone V E active serial load from N25Q00 QUAD SPI FLASH

--- Quote Start ---

Anybody has any idea if Cyclone V checks for the QSPI size when booting?

--- Quote End ---

The FPGA does not check the size, but it does do an ID check. I forget which OPCODE it uses, but its one of read ID (0x9F) or read electronic signature (silicon ID) 0xAB (you could use an oscilloscope to see which one the Cyclone V is using at power-on. I recall that the device first issues a write-disable).

Either way, in the Advanced Settings of the configuration file conversion tool, you can disable the ID check. So long as the READ (or FAST_READ) opcode matches the standard parts, it should work fine.

Cheers,

Dave

Hi Dave,

Thanks for the quick response.

I believe you are talking about Manufacturing ID (0x20) and Device ID (0xBA). They are all the same for all N25Q devices including the 64M and 1G devices. The only difference is Memory Capacity ID(0x17 for 64M and 0x21 for 1G part). Also the 1G part support all 64M part commands(OPCODEs) for backward compatibility.

I've checked with scope the what the FPGA reads from the SPI on boot and I can see that the data in both cases (64M and 1G) is read correctly (at least first several bytes that are different form 0xFF). I can try to capture more using LA, but it is going to take time.

About the idea to disable ID check - I'm not sure how to do that.

The file conversion tool does not work for generating rbf files for active serial mode.

I found that the hard way after couple of days of trying - the only way I know to get a good rbf file is to set the rbf file to be automatically generated with the sof file in the device configuration options. Is there another way to disable ID check and get good rbf file for active serial mode?

Are you sure the ID check option is for the FPGA boot or for the JTAG debugger when programs the jic file?

Thanks again,

Krassimir

Go to Spansion's FL site

http://www.spansion.com/products/memory/serial-flash/pages/spansion%20fl.aspx

click on the "Technical Documents" link and scroll down to "Connecting Spansion SPI Serial Flash to Configure Altera FPGAs"

http://www.spansion.com/support/application%20notes/configuring_altera_fpgas_via_spi_flash_an.pdf

I think that app note has the details, but I did not re-read it, so ask again if it does not :)

--- Quote Start ---

Are you sure the ID check option is for the FPGA boot or for the JTAG debugger when programs the jic file?

--- Quote End ---

Its part of the initial SPI flash byte-stream instructions. I suspect the Cyclone V performs a few instructions, reads a header, and then decides whether or not to check the previously read ID. Once you figure out how to toggle the check ID setting, you can compare the RBFs and you'll see the byte that is different. The SRunner program has lots of the flash internals documented, i.e., its the documentation for the "undocumented" features :)

You can also search the forum for threads regarding using Spansion flash, I recall it has been discussed before. For example, some of the DE0-nano boards shipped with Spansion flash and users were asking how to use it ... I think they got it figured out.

Cheers,

Dave

Hi Dave,

I've read through the Spansion app note, but there is not much relevant information there.

I also downloaded and looked the SRunner source code.

SRunner uses .rpd files to download the FPGA image. It seems to me the file is written as raw data into the EPCS flash.

Using the Convert Programming Files menu in Quartus I generated .rpd file for active serial and disabled ID check in the advanced menu. Active Serial is available as an option for .rdp files, but is not available for .rbf files.

I've compared the .rpd and .rbf files and they look the same in the beginning, but are different after that.

I've also programmed the .rpd file in the 64M FLASH, but it does not work.

I'm not sure what else to try.

It seems like the problem comes down to how to generate .rbf file for Active Serial configuration with the ID check disabled.

Thanks,

Krassimir

--- Quote Start ---

I've read through the Spansion app note, but there is not much relevant information there.

--- Quote End ---

You found the Check ID but for .rpd generation, so that must be what I was recalling. I'm pretty sure you are supposed to be using the .rpd file format, not the .rbf.

What are you using to program your flash device? Are you using a USB-Blaster via a 10-pin JTAG header, or are you using custom code? If you are using custom code, then keep in mind that the AS data stream needs its bytes in LSB-to-MSB order, whereas SPI Flash uses MSB-to-LSB. That means you have to send SPI Flash opcodes in MSB-to-LSB order, but you need to reverse the data bytes written to the flash.

Cheers,

Dave

I'm using a custom SW that runs on NIOS and downloads the .rbf file via generic UART. I'm using the USB-Blaster just to run the NIOS code.

This is all has been verified and works just fine.

I kept digging in the .rbf files and I think I found the ignore ID bit in the .rbf header.

Unfortunately the .rbf file is generated for passive serial so I can't use it directly:

Here is the beginning of the .rbf file with ID check disabled (passive serial):

00000000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000020 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000030 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000040 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000050 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000060 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000070 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000080 6A 6A 6A 6A 3E F0 FF FF 77 FD FF FF B6 F3 FF FF jjjj>ðÿÿwýÿÿ¶óÿÿ

00000090 37 F5 FF FF F6 F2 FF FF 77 F0 FF FF 33 F9 FF FF 7õÿÿöòÿÿwðÿÿ3ùÿÿ

000000A0 BA F9 FF FF 19 F0 FF FF B8 F0 FF FF 5B F5 FF FF ºùÿÿ.ðÿÿ¸ðÿÿ[õÿÿ

000000B0 79 F6 FF FF 5B F9 FF FF 59 F8 FF FF 19 F4 FF FF yöÿÿ[ùÿÿYøÿÿ.ôÿÿ

000000C0 BD F6 FF FF BD F2 FF FF 58 F4 FF FF 7C F4 FF FF ½öÿÿ½òÿÿXôÿÿ|ôÿÿ

000000D0 7F F6 FF FF 7A F2 FF FF 9D F3 FF FF 99 F0 FF FF .öÿÿzòÿÿ.óÿÿ™ðÿÿ

000000E0 BB F3 FF FF 3C F4 FF FF 18 F5 FF FF 58 F0 FF FF »óÿÿ<ôÿÿ.õÿÿXðÿÿ

000000F0 19 F0 FF FF 59 F2 FF FF 19 F0 FF FF 99 F2 FF FF .ðÿÿYòÿÿ.ðÿÿ™òÿÿ

00000100 9C F1 FF FF 19 F5 FF FF 19 F5 FF FF 4E F3 FF FF œñÿÿ.õÿÿ.õÿÿNóÿÿ

00000110 9E F7 FF FF 1A F4 FF FF EE F4 FF FF 1A F1 FF FF ž÷ÿÿ.ôÿÿîôÿÿ.ñÿÿ

00000120 6E F1 FF FF 00 00 91 F2 FF FF FF FF FF FF FF FF nñÿÿ..‘òÿÿÿÿÿÿÿÿ

Here is the .rbf file with ID check enabled (passive serial):

00000000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000020 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000030 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000040 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000050 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000060 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000070 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000080 6A 6A 6A 6A 3E F0 FF FF 77 FD FF FF B6 F3 FF FF jjjj>ðÿÿwýÿÿ¶óÿÿ

00000090 37 F5 FF FF F6 F2 FF FF 77 F0 FF FF 33 F9 FF FF 7õÿÿöòÿÿwðÿÿ3ùÿÿ

000000A0 BA F9 FF FF 11 F0 FF FF B8 F0 FF FF 5B F5 FF FF ºùÿÿ.ðÿÿ¸ðÿÿ[õÿÿ

000000B0 79 F6 FF FF 5B F9 FF FF 59 F8 FF FF 19 F4 FF FF yöÿÿ[ùÿÿYøÿÿ.ôÿÿ

000000C0 BD F6 FF FF BD F2 FF FF 58 F4 FF FF 7C F4 FF FF ½öÿÿ½òÿÿXôÿÿ|ôÿÿ

000000D0 7F F6 FF FF 7A F2 FF FF 9D F3 FF FF 99 F0 FF FF .öÿÿzòÿÿ.óÿÿ™ðÿÿ

000000E0 BB F3 FF FF 3C F4 FF FF 18 F5 FF FF 58 F0 FF FF »óÿÿ<ôÿÿ.õÿÿXðÿÿ

000000F0 19 F0 FF FF 59 F2 FF FF 19 F0 FF FF 99 F2 FF FF .ðÿÿYòÿÿ.ðÿÿ™òÿÿ

00000100 9C F1 FF FF 19 F5 FF FF 19 F5 FF FF 4E F3 FF FF œñÿÿ.õÿÿ.õÿÿNóÿÿ

00000110 9E F7 FF FF 1A F4 FF FF EE F4 FF FF 1A F1 FF FF ž÷ÿÿ.ôÿÿîôÿÿ.ñÿÿ

00000120 6E F1 FF FF 00 00 93 BA FF FF FF FF FF FF FF FF nñÿÿ..“ºÿÿÿÿÿÿÿÿ

There are 3 bytes that are different:

addr 0xA4 : 0x19 vs 0x11 - I belive this is the ID check disable/enable

addr 0x126&0x127: 0x91 0xF2 vs. 0x93 0xBA - this looks like cheksum or CRC

If the last 2 bytes are CRC or cheksum I can't figure out how to compute them.

Here is for reference how the .rbf starts when generated for Active Serial automatically with the .sof file:

00000000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000020 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000030 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000040 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000050 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000060 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000070 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ

00000080 6A 6A 6A 6A 36 F0 FF FF 77 FD FF FF B6 F3 FF FF jjjj6ðÿÿwýÿÿ¶óÿÿ

00000090 37 F5 FF FF F6 F2 FF FF 77 F0 FF FF 33 F9 FF FF 7õÿÿöòÿÿwðÿÿ3ùÿÿ

000000A0 BA F9 FF FF 11 F0 FF FF B8 F0 FF FF 5B F5 FF FF ºùÿÿ.ðÿÿ¸ðÿÿ[õÿÿ

000000B0 79 F6 FF FF 5B F9 FF FF 59 F8 FF FF 19 F4 FF FF yöÿÿ[ùÿÿYøÿÿ.ôÿÿ

000000C0 B9 F6 FF FF B9 F2 FF FF 5C F4 FF FF 78 F4 FF FF ¹öÿÿ¹òÿÿ\ôÿÿxôÿÿ

000000D0 7F F6 FF FF 7A F2 FF FF 99 F3 FF FF 99 F0 FF FF .öÿÿzòÿÿ™óÿÿ™ðÿÿ

000000E0 BB F3 FF FF 38 F4 FF FF 1C F5 FF FF 58 F0 FF FF »óÿÿ8ôÿÿ.õÿÿXðÿÿ

000000F0 19 F0 FF FF 59 F2 FF FF 19 F0 FF FF 9D F2 FF FF .ðÿÿYòÿÿ.ðÿÿ.òÿÿ

00000100 9C F1 FF FF 1D F5 FF FF 19 F5 FF FF 4E F3 FF FF œñÿÿ.õÿÿ.õÿÿNóÿÿ

00000110 98 F7 FF FF 18 F4 FF FF EC F4 FF FF 1A F1 FF FF ˜÷ÿÿ.ôÿÿìôÿÿ.ñÿÿ

00000120 6A F1 FF FF 00 00 A0 CC FF FF FF FF FF FF FF FF jñÿÿ..*Ìÿÿÿÿÿÿÿÿ

Thanks,

Krassimir

--- Quote Start ---

I'm using a custom SW that runs on NIOS and downloads the .rbf file via generic UART. I'm using the USB-Blaster just to run the NIOS code.

This is all has been verified and works just fine.

--- Quote End ---

This response is not clear. I understand that you can verify the flash, i.e., read back what you wrote. However, you did not answer the question; "Are you bit-reversing the data bytes before you write them to SPI Flash?". If you are not, then AS configuration will fail, since the data is not in the correct format expected by the FPGA configuration controller.

Can you program the EPCS device in AS mode using your USB-Blaster, or do you have another board with an AS connection to the SPI flash via a USB-Blaster? If you do, you can download that using Quartus, and read the data back using your NIOS II code, and you will see that the bytes are written to the flash in bit-reversed format. (I have an old UP3 board that I have used to confirm this).

Cheers,

Dave

Hi Dave,

Sorry I did not read carefully your question.

I think I'm doing everything you are suggesting and yes I do bit swapping.

Here is the setup:

1. I have two identical boards with Cyclone V and SPI FLASH connected to the AS pins.

2. One board has N25Q064 for FLASH- 64Mbit part.

3. The other board has N25Q00 FLASH- 1Gbit part.

4. I can program the 64Mbit FLASH with USB-Blaster and the JTAG programmer using .jic file. After power cycle the FPGA loads via AS and works just fine.

5. I can run NIOS on this board and readback the FPGA programming data. That is how I found about the bit swapping.

6. Using NIOS and my custom SW I can erase the FLASH and program the .rbf file (the NIOS SW is doing the bit swapping on the fly before writing in the FLASH).

7. After power cycle the FPGA loads via AS and works the same as when programmed with USB-Blaster and the jic file.

At this point I believe I proved I can write the .rbf file correctly in the FLASH and the .rbf file itself is good.

8. On the second board with the 1Gbit part I cannot use the USB-Blaster to program the FLASH. The JTAG programer does not recognize the 1G part and gives error.

9. I load the FPGA via JTAG and run the NIOS SW (again via JTAG).

10. Now I program the .rbf file in to the FLASH the same way I did on the board with the 64M part - the SW is absolutely the same - it uses the same OPCODES.

11. After power cycle the FPGA tries to load form the SPI FLASH (nSTATUS goes high) but it gives up after about 500us. nSTATUS goes low and then the cycle repeats. DONE pin never goes high.

I hope this answers your questions.

Thanks,

Krassimir

Hi Krassimir,

--- Quote Start ---

I hope this answers your questions.

--- Quote End ---

Yes, I agree that you appear to have done everything correctly.

So have you tried programming the .rpd image instead of the .rbf, with the check ID setting cleared?

If you can program the board with the smaller flash via .jic and set and clear the check ID bit and that board boots ok, and then repeat that test, but using the .rpd image and your custom programming sequence, then that will confirm that programming the .rpd image works fine. Then you can try programing the board with the larger flash device.

Cheers,

Dave

Hi Dave,

I did try programming the .rdp file on the 64M part that works with the .jic and .rbf files - It does not work.

I found a way to get .rbf file with ID check disabled. Looks like the .jic files are .rbf files with a jic header.

I generated .jic file and removed the jic header. The data after that is identical to the data in the .rbf file.

I actualy generated one .jic with ID check enabled and one with ID check diabled and compared both files.

Again there are only 3 bytes that are different between the two files:

addr 0xA4 : 0x19 vs 0x11 - I belive this is the ID check disable/enable

addr 0x126&0x127 which looks like checksum

Here is the test I did this time:

1. I opened the .jic file with the ID check disabled in a hex editor, removed the jic header (removed the first 158 bytes) and saved it as .rbf file.

2. On the board with the 64M part, loaded the FPGA via JTAG and booted NIOS via JTAG.

3. Erased the FLASH and programmed the .rbf file (essentially the .jic file with the jic header removed) using my NIOS custom code that does the bit swapping.

4. After power cycle the FPGA loads via AS and works the same as when programmed with USB-Blaster and the jic file.

Repeated the same on the board with the 1G part - It did not work.

After power cycle the FPGA tries to load form the SPI FLASH (nSTATUS goes high) but it gives up pretty fast, nSTATUS goes low and then the cycle repeats. DONE pin never goes high.

Any other idea to try?

Thanks,

Krassimir