Honored Contributor
Honored ContributorHi Dave,
I did try programming the .rdp file on the 64M part that works with the .jic and .rbf files - It does not work. I found a way to get .rbf file with ID check disabled. Looks like the .jic files are .rbf files with a jic header. I generated .jic file and removed the jic header. The data after that is identical to the data in the .rbf file. I actualy generated one .jic with ID check enabled and one with ID check diabled and compared both files. Again there are only 3 bytes that are different between the two files: addr 0xA4 : 0x19 vs 0x11 - I belive this is the ID check disable/enable addr 0x126&0x127 which looks like checksum Here is the test I did this time: 1. I opened the .jic file with the ID check disabled in a hex editor, removed the jic header (removed the first 158 bytes) and saved it as .rbf file. 2. On the board with the 64M part, loaded the FPGA via JTAG and booted NIOS via JTAG. 3. Erased the FLASH and programmed the .rbf file (essentially the .jic file with the jic header removed) using my NIOS custom code that does the bit swapping. 4. After power cycle the FPGA loads via AS and works the same as when programmed with USB-Blaster and the jic file. Repeated the same on the board with the 1G part - It did not work. After power cycle the FPGA tries to load form the SPI FLASH (nSTATUS goes high) but it gives up pretty fast, nSTATUS goes low and then the cycle repeats. DONE pin never goes high. Any other idea to try? Thanks, Krassimir
