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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cyclone V E active serial load from N25Q00 QUAD SPI FLASH

Hi All,

I'm trying to use Micron N25Q00 1Gbit serial QUAD SPI FLASH to load Cyclone V E (A7) using active serial interface.

I currently have boards that have Cyclone V 5CEFA7U19C8 and are loading from N25Q064 via active serial interface, but we need a lot more FLASH.

Quartus II 13.1 does not support 1Gbit QSPI devices so I have my own QSPI controller (using the dedicated active serial pins) that can read and program N25Q00 from NIOS.

I verified I can reliably read and program both N25Q00 and N25Q064 devices.

I'm using .rbf file and downloading it to the QSPI via UART. I can also read back and verify the downloaded rbf. The rbf file is generated for active serial mode.

When I use a board with N25Q064 (64Mbit), Cyclone V boots and works just fine.

Downloading the same rbf file to a board with N25Q00 (1Gbit) does not work. The FPGA constantly tries to load over the SPI interface and fails.

I've tried both x1 and x4 mode and different clock speeds. They all work on the 64Mbit, but not on the 1Gbit part.

I also verified that the rbf file do not change based on the EPCQ size selected. I can load rbf file generated for EPCQ256 on 64Mbit part and it works just fine.

Besides memory size, all other parameters are the same between the 64M part and the 1G part.

The 1G part supports 4 byte address, but by default works in 3 byte address mode and looks like and can access the first 128Mbits. The FPGA image is compressed and is under 20Mbits so it does not cross segment boundary. Supposedly Cyclone V supports EPCQ256 which supports 4 byte address and the only difference is that it has one die vs. 4 dies for N25Q00.

Anybody has any idea if Cyclone V checks for the QSPI size when booting?

Any other thought or suggestions that can help understand the problem will be highly appreciated.

Thanks!

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Any other idea to try?

    --- Quote End ---

    How about tracing the SPI flash sequence? The only thing I can guess is that perhaps your 1G flash is not responding correctly, eg., perhaps your NIOS II software is in fact "smarter" than the Cyclone V configuration manager, in that you are using 4-byte addressing when programming and reading, but the Cyclone V is not, and its only issuing 3-byte addresses ...

    Do you have a logic analyzer, or another FPGA board that you can instantiate a SignalTap II instance, and the skill to solder some wires onto the SPI flash pins (unless of course you have a 10-pin AS header you can use directly)?

    That would be what I'd try next ...

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    I am glad someone has managed to get a C5 to program an EPCQ by .jic. Every way I try I get an ID fail from the EPCQ. Did you have to do anything unusual to get it to work?. I am using an EBV SoCrates board with a 5CSXFC6C and an EPCQ256 if it is relevant.

    Thanks

    Simon Exelby
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Do you have a logic analyzer, or another FPGA board that you can instantiate a SignalTap II instance, and the skill to solder some wires onto the SPI flash pins (unless of course you have a 10-pin AS header you can use directly)?

    That would be what I'd try next ...

    --- Quote End ---

    Any updates on this topic?