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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V build fails due to missing DDR3 files

I am trying to build a Cyclone V design (QPS 20.1.1 on Win10) and getting the following error messages:

Error (12006): Node instance "s0" instantiates undefined entity "ddr3_v20_s0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "dmaster" instantiates undefined entity "ddr3_v20_dmaster". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "c0" instantiates undefined entity "ddr3_v20_c0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "oct0" instantiates undefined entity "altera_mem_if_oct_cyclonev". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "dll0" instantiates undefined entity "altera_mem_if_dll_cyclonev". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Error (12006): Node instance "mm_interconnect_0" instantiates undefined entity "ddr3_v20_mm_interconnect_0". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

All of these entities are instantiated in variation_name_0002.v; the entity names are defined in the .qip file, but there are no corresponding verilog or systemverilog files/modules in the created design database.

3 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi sir,

    I'm Adzim. Thanks for using the Intel Community.

    Can you explain more on your problem?

    How do you generate the error? Where is it appear?

    Thanks,

    Adzim

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    The easiest thing to try first is to regenerate the IP. You can reopen the parameter editor for each instance and regenerate.

    The fact that mm_interconnect is listed makes me think you are using Platform Designer. Are you? If so, make sure either the .qsys file or the .qip file generated by Platform Designer is added to the Quartus project.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi sir,


    I hope you're doing well.


    Do you still have the issue in your design?


    Regards,

    Adzim