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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V Avalon MM DMA PCIe does not export MSI Control signals

have a Cyclone V design with Avalon-mm DMA hard IP PCIe endpoint. I have enabled MSI (but have not enabled MSI-X). The generated core provides MSIIntfc_o[81:0] and MSIXIntfc_o[15:0], but does not p...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

The Cyclone V Avalon MM DMA PCIe IP was obsoleted. The MSIControl_o is not available in the Avalon-MM DMA IP PCIe endpoint, what you can do is probably build a module that uses only the MSIintfc_o signals and write to the TXs port when an interrupt condition occurs, and not having the multiple message capability provided by MSICcontrol_o.


Regards -SK


  • Seadog's avatar
    Seadog
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    SK,

    Thanks for your response.

    My workaround was to provide a shadow register where S/W can store a copy of the Message Control field from the MSI capability structure. Then I don't need the MSIControl_o signals.

    But what concerns me now is your information that the Cyclone V Avalon -MM DMA PCIe endpoint is obsolete. The IP is available to instantiate in a Qsys block, which I did; and I instantiated the Qsys block in a top-level design, and did a build in Quartus, and produced .sof and .pof files for the completed build.

    But you also seem to be saying that I can still use the Cyclone V Avalon-MM DMA PCIe endpoint, even though it is obsolete. And it seems that the obsolescence of the core is unrelated to the missing MSIControl_o signals, which I am guessing were missing before the core became obsolete?

    Thanks and regards,

    Seadog