Forum Discussion
Occasional ContributorCyclone V: A PLL with multiple clocks and independently adjusting phase of a clock
I have a PLL with 5 output clocks.
4 are at 56.25MHz and a fifth is at 225MHz that is used to sample the other outputs to confirm any phase shift in Signal Tap.
The tick-box for "Enable access to dynamic phase shift ports" is ticked.
PLL Mode: Integer-N PLL
Reference Clock Frequency 50.0MHz
Operation Mode: direct
M-Counter: 9
N-Counter: 1
C-Counter: 8, 8, 8, 8, 2 (for each outclk respectively)
Some observations:
The datasheets say that the phase can be incremented in clock period/8. The actual shift seems to be a fraction of this.
As the attached waveforms suggests:
When there is an increment in phase, it seems that other clocks move in phase too, not just the selected clock output.
Why is this happening, and how do I shift the phase of clock independently?
20 Replies
FvMSuper Contributor
Hi,
I can't recognize that more than PLL output is phase shifted in the signal tap recording. With countsel=1, only C1 phase should be affected.
Phase shift increment is 1/8 of VCO period, usually less than output clock period.
MikexxMany thanks for your reply.
Yes, the phase increments are associated with the VCO period, so where the clock is divided by 8 from the VCO frequency I would expect 64 counts for a full clock cycle for outputs 0-3. I can confirm 32 counts gets me inverted clocks.
Please have a look at the area highlighted in the attached diagram. I would expect only output 1 to change from a change in C1.
In practice I hope you can see that clock outputs 0, 1 and 3 change. I'm using clock output 4 as a reference so it is always possible it is this clock 4 and clock 2 are actually the ones that have changed phase.
Either way the PLL isn't behaving as expected. Or it isn't clear which C-clock counts tally with which clock output.
