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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock

I have a PLL with 5 output clocks. 4 are at 56.25MHz and a fifth is at 225MHz that is used to sample the other outputs to confirm any phase shift in Signal Tap. The tick-box for "Enable access to ...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago
Hi,
I can't recognize that more than PLL output is phase shifted in the signal tap recording. With countsel=1, only C1 phase should be affected.

Phase shift increment is 1/8 of VCO period, usually less than output clock period.
Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Many thanks for your reply.

Yes, the phase increments are associated with the VCO period, so where the clock is divided by 8 from the VCO frequency I would expect 64 counts for a full clock cycle for outputs 0-3. I can confirm 32 counts gets me inverted clocks.

Please have a look at the area highlighted in the attached diagram. I would expect only output 1 to change from a change in C1.

In practice I hope you can see that clock outputs 0, 1 and 3 change. I'm using clock output 4 as a reference so it is always possible it is this clock 4 and clock 2 are actually the ones that have changed phase.

Either way the PLL isn't behaving as expected. Or it isn't clear which C-clock counts tally with which clock output.