Cyclone V 12bit LVDS deserialisation.

I'm using x6 SERDES and combining 2x6Bit to 12 Bit output at half slowclock rate. 12-Bit ADC with LVDS output at 480 MHz LVDS/40 MHz output data rate.

   LVDSCLK : altera_pll
	GENERIC MAP
	(
		operation_mode => "lvds",
		reference_clock_frequency => "40.0 MHz",
		number_of_clocks => 4,
		output_clock_frequency0 => "480.0 MHz",
		phase_shift0 => "1041 ps",
		duty_cycle0 => 50,
		output_clock_frequency1 => "80.0 MHz",
		phase_shift1 => "-5208 ps",
		duty_cycle1 => 50,
		output_clock_frequency2 => "80.0 MHz",
		phase_shift2 => "4167 ps",
		duty_cycle2 => 17,
		output_clock_frequency3 => "40.0 MHz",
		phase_shift3 => "7292 ps",
		duty_cycle3 => 50
	)
	PORT MAP
	(
		rst => reset,
		refclk => AD9222_FCO,
		outclk(0) => fastclock, -- 180° 1041 ps
		outclk(1) => slowclock, -- 210° -5208 ps
		outclk(2) => enaclock,  -- 120° 4167 ps
		outclk(3) => outclock,
		locked => rx_locked
	);
chan:
FOR I IN 0 TO N_AD_CHAN - 1 GENERATE
	ALTLVDS_RX_component : ALTLVDS_RX
	GENERIC MAP (
		buffer_implementation => "RAM",
		cds_mode => "UNUSED",
		common_rx_tx_pll => "ON",
		data_align_rollover => 4,
		data_rate => "480.0 Mbps",
		deserialization_factor => 6,
		dpa_initial_phase_value => 0,
		dpll_lock_count => 0,
		dpll_lock_window => 0,
		enable_clock_pin_mode => "UNUSED",
		enable_dpa_align_to_rising_edge_only => "OFF",
		enable_dpa_calibration => "ON",
		enable_dpa_fifo => "UNUSED",
		enable_dpa_initial_phase_selection => "OFF",
		enable_dpa_mode => "OFF",
		enable_dpa_pll_calibration => "OFF",
		enable_soft_cdr_mode => "OFF",
		implement_in_les => "OFF",
		inclock_boost => 0,
		inclock_data_alignment => "EDGE_ALIGNED",
		inclock_period => 25000,
		inclock_phase_shift => 0,
		input_data_rate => 480,
		intended_device_family => "Cyclone V",
		lose_lock_on_one_change => "UNUSED",
		lpm_hint => "CBX_MODULE_PREFIX=lvds",
		lpm_type => "altlvds_rx",
		number_of_channels => 1,
		outclock_resource => "AUTO",
		pll_operation_mode => "NORMAL",
		pll_self_reset_on_loss_lock => "ON",
		port_rx_channel_data_align => "PORT_UNUSED",
		port_rx_data_align => "PORT_UNUSED",
		refclk_frequency => "40.000000 MHz",
		registered_data_align_input => "UNUSED",
		registered_output => "OFF",
		reset_fifo_at_first_lock => "UNUSED",
		rx_align_data_reg => "RISING_EDGE",
		sim_dpa_is_negative_ppm_drift => "OFF",
		sim_dpa_net_ppm_variation => 0,
		sim_dpa_output_clock_phase_shift => 0,
		use_coreclock_input => "OFF",
		use_dpll_rawperror => "OFF",
		use_external_pll => "ON",
		use_no_phase_shift => "ON",
		x_on_bitslip => "ON"
		--clk_src_is_pll => "off"
	)
	PORT MAP (
		rx_enable => enaclock,
		rx_in => AD9222_D(I TO I),
		rx_inclock => fastclock,
		rx_out => rx_out(I)
	);
	PROCESS (slowclock, reset)
	BEGIN
      IF rising_edge(slowclock) THEN
         reg1(I) <= rx_out(I);
         reg2(I) <= reg1(I);
         reg3(I) <= reg2(I);
		END IF;
	END PROCESS;
	PROCESS (outclock, reset)
	BEGIN
	   IF reset = '1' THEN
	      lvds_rx(I) <= (others => '0');
      ELSIF rising_edge(outclock) THEN
         lvds_rx(I) <= reg2(i) & reg1(i);
		END IF;
	END PROCESS;

If your data rate is reasonable you can always write your own deserializer code and make it any length you want.