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Altera_Forum
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14 years ago

Cyclone IV pin connection Guide line make confuse

Hi all,

I am using document number PCG-01008- 1.3 (pin connection guide line of Cyclone IV) as main reference for board design. In Clock and PLL Pins section, there is Connection Guidelines: "In Clone IV GX devices, the pin should be AC-coupled if used as optional high speed differential reference clock input"

i tried and could not find any reason for this recommend (AC coupled for Reference clock), it is not persuaded. I found reference design of Altera, document number: 150-0311003-A1 (Cyclone IV GX FPGA Development Kit Board" that just use DC coupled for Serdes reference clock, it is not match with pin connection guideline document.

Could any one give any reason for this?

Thanks,

Sonkiet

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    In my opinion, the cyclone IV device manual is very clear about the required coupling for the GX transceiver reference clock. It requires AC coupling for all source IO standards, except for PCIe HCSL, that is DC coupled. See e.g. Volume 2, page 1-22, Table 1–5. REFCLK I/O Standard Support.

    If the DC coupled clock on the DevKit is not HCSL standard, it would in fact contradict the manual.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks FvM.

    I see the manual indicate that AC couple for differential IO standard such LVDS and LVPECL. However, as you see, in development kit, the LVDS buffer ICS8543 was used and make DC couple to reference clock pin of Bank 8B (REFCLK4N/P) which is terminated to 100 Ohm.

    I think there is no reason to just do AC couple for LVDS and LVPECL signal. It can not acceptable, because using AC couple, we need more resistors to do that than DC couple.

    See attachment file. So, there is any limitation @ this point of Cyclone IV?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Thanks FvM.

    I see the manual indicate that AC couple for differential IO standard such LVDS and LVPECL. However, as you see, in development kit, the LVDS buffer ICS8543 was used and make DC couple to reference clock pin of Bank 8B (REFCLK4N/P) which is terminated to 100 Ohm.

    I think there is no reason to just do AC couple for LVDS and LVPECL signal. It can not acceptable, because using AC couple, we need more resistors to do that than DC couple.

    See attachment file. So, there is any limitation @ this point of Cyclone IV?

    Thanks

    --- Quote End ---

    it is great informative post. thanks for helped me out
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I guess the reason for AC-coupling requirement is that common voltage level from the clock source might be incompatible with REFCLK input. But if you know what you're doing there is nothing wrong in using DC-coupled connection to REFCLK.