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Altera_Forum
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14 years ago

Cyclone IV pin connection Guide line make confuse

Hi all, I am using document number PCG-01008- 1.3 (pin connection guide line of Cyclone IV) as main reference for board design. In Clock and PLL Pins section, there is Connection Guidelines: "In C...
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Altera_Forum
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14 years ago

Thanks FvM.

I see the manual indicate that AC couple for differential IO standard such LVDS and LVPECL. However, as you see, in development kit, the LVDS buffer ICS8543 was used and make DC couple to reference clock pin of Bank 8B (REFCLK4N/P) which is terminated to 100 Ohm.

I think there is no reason to just do AC couple for LVDS and LVPECL signal. It can not acceptable, because using AC couple, we need more resistors to do that than DC couple.

See attachment file. So, there is any limitation @ this point of Cyclone IV?

Thanks