Cyclone IV GXB vs dual-purpose differential transmitter/receiver channels

If your LVDS signal rates are ~800Mbps or slower, and since you plan on coding everything yourself, you should use the LVDS pins on the device.

The transceiver channels cannot be used without instantiating ALTGX and ALTGX_RECONFIG functions; even to assign pins you must have these blocks!

Cheers,

Dave

Thank you for your reply

I tried compiling my firmware in quartus and there is no problev for the "tx" side of GXB to be configured as standard LVDS (under pin assgiement in Quartus v11). I can live with that, since i have only downstream of data. In this case will i be able to capture data coming through GXB channel.

Also can i use "rx" side of GXB as General Purpose output?

Regards

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I tried compiling my firmware in quartus and there is no problev for the "tx" side of GXB to be configured as standard LVDS (under pin assgiement in Quartus v11).

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The Cyclone IV GX Starter kit uses the following transceiver pins:

#  Transceivers (SGMII interface or SMA interface)
set pin(enet_tx)      {PIN = C2, IOSTD = "1.5-V PCML"}
set pin(enet_tx(n))   {PIN = C1}
set pin(enet_rx)      {PIN = E2, IOSTD = "1.5-V PCML"}
set pin(enet_rx(n))   {PIN = E1}
#  PCIe Transceivers
set pin(pcie_tx)        {PIN = G2,  IOSTD = "1.5-V PCML"}
set pin(pcie_tx(n))     {PIN = G1}
set pin(pcie_rx)        {PIN = J2,  IOSTD = "1.5-V PCML"}
set pin(pcie_rx(n))     {PIN = J1}

Which pins were your "tx" signal using?

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Also can i use "rx" side of GXB as General Purpose output?

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I don't think so. I believe it needs to be driven from the ALTGX component. Try using the pins for GPIO in Quartus and let it make the ultimate decision :)

Cheers,

Dave

Hi

I just noticed that i was writing wrong. The "rx" side of GXB gives no problem in Quartus when assigenet as LVDS. Sorry about that.

I exported pin assigement in Quartus. Here is the pin definitions of signals in question

To,Direction,Location,I/O Bank,VREF Group,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair
LVDS_CLK1_in,Input,PIN_E7,8A,B8_N0,LVDS,,,,LVDS_CLK1_in(n)
LVDS_CLK1_in(n),Input,PIN_E6,8A,B8_N0,LVDS,,,,LVDS_CLK1_in
LVDS_DATA0_in,Input,PIN_J2,QL0,,LVDS,,,,LVDS_DATA0_in(n)
LVDS_DATA0_in(n),Input,PIN_J1,QL0,,LVDS,,,,LVDS_DATA0_in
LVDS_DATA1_in,Input,PIN_E2,QL0,,LVDS,,,,LVDS_DATA1_in(n)
LVDS_DATA1_in(n),Input,PIN_E1,QL0,,LVDS,,,,LVDS_DATA1_in

for the "I/O Standard" you can see that i am using LVDS and Qv11.0 does not complain.

For the transmission over GXB i can use only 1.5 PCMA standard or 2.5V "default"

regards

Let me edit your pin details ...

#  REFCLK input
LVDS_CLK1_in        PIN_E7
LVDS_CLK1_in(n)     PIN_E6
#  Transceiver input
LVDS_DATA0_in      PIN_J2
LVDS_DATA0_in(n)   PIN_J1
#  Transceiver input
LVDS_DATA1_in      PIN_E2
LVDS_DATA1_in(n)   PIN_E1

Ok, so these are all inputs.

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for the "I/O Standard" you can see that i am using LVDS and Qv11.0 does not complain.

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Ok, for inputs Quartus is not complaining.

Make sure to check your outputs too :)

Cheers,

Dave

Hi

Thank you for correcting my code ... i am new here and these are my first posts.

In transmission ( "tx" ) over the GXB, Quartus offers (for pins G2-G1 or C2-C1) only "1.5-V PCML" or 2.5V default. I am seeing that only 1.5V-PCML has differential output. Can I from my VHDL code write to this channel then?

Thanks

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In transmission ( "tx" ) over the GXB, Quartus offers (for pins G2-G1 or C2-C1) only "1.5-V PCML" or 2.5V default. I am seeing that only 1.5V-PCML has differential output. Can I from my VHDL code write to this channel then?

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Yes, you can write VHDL to control those channels. Whether or not you can do that directly with VHDL, or indirectly via ALTGX is one question. Quartus can answer this for you; just try it.

However, you indicated you want to communicate with an LVDS component. You would need to confirm whether PCML levels are compatible with your "LVDS" component. For example, it might be able to support more than just LVDS logic levels. I often use Micrel parts that have 'Any Differential' inputs.

If you are transmitting an encoded signal, then you might be able to AC-couple the PCML output and LVDS receiver.

Without knowing what you are actually trying to communicate with, its a bit hard to offer suggestions. Try to explain your application in a bit more detail.

Cheers,

Dave

Hi

you are wright. For transmission i will have to have use some sort of buffer cml-> lvds.

Basically my system has two fpga boards. On one board there is a ccd sensor connected to fpga1. Fpga1 then downstreams pixels through LVDS to the second board. On second board i have fpga2 (cyclon iv gx) and usb device to transfer data to pc. As you have noticed, between fpga1 and fpga2 there is lvds connection. Fpga1 produces clock, sync and data signal (clk1, data1 and data0 in my previous post) which are coded by me. The upstream signal from fpga2->fpga1 is needed only for synchronization (it is only a pulse generated every 15ms). But i want to send it through GXB because i am short on GPIOs.

I am looking for cml-->lvds buffers. I haven't found any yet.

Regards

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I am looking for cml-->lvds buffers. I haven't found any yet.

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Look on Micrel's web site, eg.,

http://www.micrel.com/page.do?page=product-info/translators.jsp

Cheers,

Dave

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The upstream signal from fpga2->fpga1 is needed only for synchronization (it is only a pulse generated every 15ms). But i want to send it through GXB because i am short on GPIOs.

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Keep in mind that using the GXB channels might not be a simple matter of just toggling the I/O pin.

For example, if you are forced to use the ALTGX component, and it has a minimum data rate of say 1Gbps, then you will have to construct your pulse from a serial bit stream.

For example, if you want a 1ms long pulse every 15ms, at a transceiver lane rate of 1Gbps (1ns per bit), you'll need to transmit 1e6 ones followed by 14e6 zeros. You could actually generate your pulse at a lower clock frequency and then serialize it, i.e., oversample a 1-bit signal in the FPGA by 1000x.

The point is it might be a little more complicated. Make sure to synthesize a design to check whether you can do it the easy way, or the hard way :)

Cheers.

Dave