Cyclone IV E – PLL Power Track Width Recommendation Clarification

Hi,

I am working on a design that uses the Cyclone IV E FPGA, and I’ve been following the Altera/Intel board design guidelines for PLL power routing. The document recommends using a minimum 20 mil trace width for the PLL power supply routing.

Due to space constraints on our PCB, we have routed the PLL supply net as follows:

• From the ferrite bead to the FPGA cutout: 20 mil trace width
• After the cutout region leading into the FPGA power pin area: reduced to 6 mil trace width

My questions are:

1. Is it acceptable to reduce the PLL power trace width from 20 mil to 6 mil after the cutout region?
2. If not, what issues might arise due to this narrower trace?

I have attached a snapshot from the guideline for reference.

Requesting your comments and guidance on whether this implementation is safe or if the narrower section could cause problems with PLL performance.

Thanks in advance!