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YogeshaDG's avatar
YogeshaDG
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5 days ago

Cyclone IV E – PLL Power Track Width Recommendation Clarification

Hi, I am working on a design that uses the Cyclone IV E FPGA, and I’ve been following the Altera/Intel board design guidelines for PLL power routing. The document recommends using a minimum 20 mil t...
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Farabi's avatar
Farabi
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18 hours ago

Hello, 

 

6mil is normally for signal trace. Recommended power trace for PLL is 20mil, however it also depends on your how fast you want the PLL to run. 

PLL power is only critical for high speed clock. The impact if the power delivery is not good to PLL during transmission, the clock signal will not clean, and maybe take longer time to lock. 

 

regards,

Farabi

  • YogeshaDG's avatar
    YogeshaDG
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    15 hours ago

    Hi, thanks for your response.

    In our design, the maximum clock frequency is 33 MHz, and the FPGA uses a 1 mm ball‑pitch package. Due to this, we are able to route the PLL net using a 20 mil trace width after the filtering section.

    From the filter output up to the FPGA cut‑out, the trace width remains at 20 mil.
    Inside the cut‑out, from the cut‑out region to the FPGA ball, the trace width is reduced to 6 mil to meet the package escape routing constraints.

    Regards,

    Yogesh