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Altera_Forum
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12 years ago

Cyclone IV AS and JTAG programming at different voltage levels

I have some questions regarding the programming of Cyclone IV devices as shown in figure 8-28 in the datasheet. In my case, the banks where all programming pins reside (1, 2, 5 and 6) are all 2.5V.

For the AS configuration mode, nSTATUS, CONF_DONE and nCONFIG are pulled to 2.5V while the rest of the pins reside in 2.5V banks. Because the serial configuration device (min. 2.7V, datasheet) and AS header are connected to 3.3V, all programming pins on the Cyclone IV side will be driven with 3.3V levels. According to table 1-3 in the datasheet, Recommended Operating Conditions, all pins can operate up to 3.6V so this setup should work fine. Also according to an447 this should be OK because any overshoot will be clamped by the PCI diode.

1. Has anyone tried this configuration at these voltage levels? It looks unsafe to me using a clamping diode without any current limitation (series resistor). Even neglecting any overshoot, DC driving at 3.3V would result in a 0.8V voltage drop on the PCI diode. Seems like enough to exceed the 10mA these diodes can handle. Maybe I'm missing something but can't figure out what (very low dI/dV of the PCI diode maybe?)

2. According to figure 8-28, the JTAG header must be connected to 2.5V VCCA. What is the reason for 2.5V and not 3.3V for instance? Can I connect the JTAG header to 3.3V and use external clamping diodes to 3.3V making sure i'm enough far away from the 4.1V absolute max?

3. The nCSO and ASDO pins are used for LVDS signals. These pins are also connected to the serial configuration device, external clamping diode, 10pf cap and AS connector. Doesn't this degrade the performance of these LVDS lines at high speed?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    1. You can get rid of the AS header and all related overvoltage problems by using indirect JTAG programming for the AS configuration device.

    2. I prefer 3.3V supply and external schottky clamp diodes with series resistors for the JTAG header. It's quite clear that the 2.5V supply recommendation is a concession to overvoltage sensitivity and the fact, that some Altera programming adapters are driving the JTAG lines with rather low impedance and respective overshoot.

    --- Quote Start ---

    3. The nCSO and ASDO pins are used for LVDS signals

    --- Quote End ---

    With connected AS flash? Doesn't sound like a good idea.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    1. You can get rid of the AS header and all related overvoltage problems by using indirect JTAG programming for the AS configuration device.

    --- Quote End ---

    Mox, just take a look at Fig. 8-29 on the next page.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you FvM and Aphraton for your quick answers and tips!

    @ FvM

    It is not a good idea indeed. According to the datasheet, EPCS devices have 10uA leakage current and 8pF input capacitance (+ trace load etc). This will probably result in asymmetry between the two LVDS lines and very poor signal quality. Beside this, are you aware of any physical damage to any of the devices when nCSO and ASDO connected to an AS device are also used as LVDS?