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Honored Contributor
Honored ContributorCyclone III stuck at POR?
Hi,
I have problems to get a custom board work, the FPGA seems to be stuck in POR. It's a PCIe card with a EP3C10F256C7N. I attached an excerpt of the schematic to this post. I have 10 prototype boards, they all show the same problem: nSTATUS is at LOW level and we can't test the boards with JTAG. It's our the second design with a Cyclone III, the first one worked well. I checked the power supplies, they are well inside the limits. VCCINT is 1.196V, VCCA is 2.497V and VCCIO is 3,282V. I tried to vary VCCA and VCCIO some 0.1V up and down, but without success. VCCIO is sourced directly from the 3.3V of PCIe connector, VCCINT and VCCA are made from this 3.3V with linear regulators. All VCCIO are tied together to the same 3.3V power supply. MSEL[2:0] is set to 010, that should be AS standard POR with 3.3V configuration voltage. I measured the config and JTAG pins: nCONFIG: 3.3V nSTATUS: 0V CONF_DONE: 0V nCEO: 0.2V (open?) DCLK: 3.3V nCE: 0.9V (?) nCSO: 3.3V ASDO: 3.3V DATA[0]: 3.3V TDO: 3.3V TDI: 3.3V TMS: 3.3V TCK: 0V Can nCE or any other config pin hold the device in POR? The design has migration parts (EP3C5, EP3C16 and EP3C25), therefore I have more VCC and GND pins than required for the EP3C10 connected to the device. I checked all dedicated pins (configuration and power) against a Quartus II 10.1 generated pin list. I compared it with our schematic and with the PCB artwork, but I can't find any mistake. I didn't check all of the I/O connected to the board, but all peripheral devices are powered from 3.3V, so I assume that they're within the I/O limits. Where is the mistake? What other reason can hold the device in POR? Regards, Jürgen35 Replies
Altera_ForumThat fixed it! Thanks!
Now, I wonder if Jurgen did the same thing.- Altera_Forum
You stumbled upon one of the popular Cyclone III design faults. There's a good chance to fix it, Altera board users even reported to have connected the exposed pad by drilling a hole from the bottom and soldering a small wire to the pad.
P.S.: http://www.alteraforum.com/forum/showthread.php?t=4999 http://www.alteraforum.com/forum/showthread.php?t=4065 - Altera_Forum
Exposed Pad pin 145? I missed this. I went back and found reference to it in these locations...
- AN 466: Cyclone III Design Guidelines, Page 3, note (5) "The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane on your PCB. This exposed pad is used for electrical connectivity and not for thermal purposes." - Pin Information for the Cyclone III EP3C5 Device, page 7, note 3 "The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane on your PCB. This exposed pad is used for electrical connectivity, and not for thermal purposes." - Altera Cyclone III Handbook, Chapter 1, Page 1-4 "The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane on your PCB. This exposed pad is used for electrical connectivity, and not for thermal purposes." footprint information - http://www.altera.com/devicepackaging/04r00221-02.pdf I think I can salvage these protoboards with a little bit of solder work since it calls for electrical connectivity and not thermal performance. I'll report back early next week and let you know for sure that this worked for me. I'm sure it will. Thanks so much for noticing this. - Altera_Forum
Oh man, if there's a pin 145 exposed pad, then that could be the problem. Thanks for noticing that!
I'll work on this and let you know what I find. - Altera_Forum--- Quote Start --- Here are what I think are the relevant pages from my schematic. --- Quote End --- The exposed pad ("pin145") isn't connected in your schematic, I hope you did it otherwise.
- Altera_Forum
Downloaded the most recent handbook, in case my copy was too old.
VCC specs I saw in the handbook... VCC must rise monotonically with no plateaus - checked that with a scope. Each individual power supply should reach the recommended operating range within 50 ms - checked that too. - Altera_Forum--- Quote Start --- Sorry, I have to ask. What is the JTAG tool you are talking about? --- Quote End --- Quartus->Tools->JTAG Chain Debugger
- Altera_Forum
Here are what I think are the relevant pages from my schematic.
- Altera_Forum
The POR circuit keeps the device in the reset state until the power supply voltage levels have stabilized after device power-up. After device power-up, the device does not release nSTATUS until the required voltages listed in Table 9-4 on page 9-8 are above the POR trip point of the device.
For the Cyclone III, voltage that must be powered-up are VCCINT, VCCA, VCCIO (for the banks in which the configuration and JTAG pins reside) In my application I have the following voltages: VCCINT 1.2 (actual is 1.209) VCCA 2.5 (actual is 2.508) VCCIO 3.3 (actual is 3.255) So, I believe I have the voltages required. - Altera_Forum--- Quote Start --- There isn't a JTAG reset pin, so you should always be able to access the JTAG chain. --- Quote End --- At least C III, but I guess other Altera FPGAs too, are actually blocking JTAG access when a reset condition exists, e.g. one of the monitored supply voltages is below it's POR threshold.
