Forum Discussion
Cyclone III slave (PS) embedded memory errors
- 3 years ago
I think I've found the problem.
There is a trace connected to pin 76 on the master and pin 99 on the slave. Trace is pulled up to 3.3V via 2.2k
This **bleep** resistor was dead, and the trace was actually floating.
I didn't use this pins before, so I can't reveal the resistor is dead.
As I start to use it, all logic became a total mess. Something worked, something not. By elimination I found the culprit.
I can't explain how this trace connected with loading errors (when FPGA not even in user mode), but the fact is - replacing resistor solved all problems, ROMs working now (though I don't use them anymore).
Thanks to all, problem solved!
Thanks for detailed explanation. Your conclusions are plausible, sounds like at least the memory initialization part of the configuration bit stream has insufficient consistency check.
Frank
P.S. According to my experience, double edges caused by ringing clock signal is the most popular signal integrity problem related to configuration. Series resistors providing source side termination can be essential to get clean clock.
@FvM wrote:
Series resistors providing source side termination can be essential to get clean clock.
Thanks, but I've tried that already.
I've tried to remove buffers and change them to zero Ohm resistors - no changes.
Then I've replaced 0R resistors to 51R ones - no changes.
Then I've put buffers back, cut traces afters them (which are facing to the slave), and put 51R there in series. No changes.
Maybe it should'n be 51R, but smth bigger? Or smaller?
The situation is aggravated by the fact that I have nothing except soldering iron and multimeter )
I'm about to give up actually...