Forum Discussion

Vic3Dexe's avatar
Vic3Dexe
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Cyclone III slave (PS) embedded memory errors

I have two Cyc III devices (master-slave, AS and PS respectively) + EPCS16 flash. In both devices I have ROMs (megafunction), one in the master and two of them in the slave. All ROMs are initialize...
  • Vic3Dexe's avatar
    Vic3Dexe
    3 years ago

    I think I've found the problem.

    There is a trace connected to pin 76 on the master and pin 99 on the slave. Trace is pulled up to 3.3V via 2.2k

    This **bleep** resistor was dead, and the trace was actually floating.

    I didn't use this pins before, so I can't reveal the resistor is dead.

    As I start to use it, all logic became a total mess. Something worked, something not. By elimination I found the culprit.

    I can't explain how this trace connected with loading errors (when FPGA not even in user mode), but the fact is - replacing resistor solved all problems, ROMs working now (though I don't use them anymore).

    Thanks to all, problem solved!

Vic3Dexe's avatar
Vic3Dexe
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

There is the ROM1 content in the slave after power up:

Then I do "Import data from the file" and use the same .mif file used for ROM init:

Red numbers shows the differences. Then "Write data to in-system memory", read it back again, and "Import data from file" again:

As you can see, all numbers which were red, now are consistent with actual .mif file.

  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    4 years ago

    Hi Vic3Dexe,

    can you please provide total procedure you are following (bit file generation, bit file loading, loads from EPCS, etc..)

    • Vic3Dexe's avatar
      Vic3Dexe
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      1. MIF files were generated only once. I don't change them. They are constant. It's irrelevant how they are maked, because they don't change.

      2. I have 2 projects in Quartus (13 sp1 web version) - one for master, and one for slave.

      3. In both projects I've created "ROM 1-port" megafunctions (1 for master, and 2 of them for slave) and set according .mif files as init values. Like this:

      4. Compiled (or fully recompiled) both projects, so the result is two .sof files.

      5. Used convert programming file tool to create .pof file:

      6. Used programmer to write EPCS:

      Here is the quartus log (one of the million attemp to get it to work). Verification also always passes (if enabled).

      Info (209060): Started Programmer operation at Tue Jun 21 17:23:18 2022
Info (209018): Device 1 silicon ID is 0x14
Info (209044): Erasing ASP configuration device(s)
Info (209024): Programming device 1
Info (209018): Device 1 silicon ID is 0x14
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Tue Jun 21 17:25:47 2022

      7. Power up/reset the board. Both devices loads its content from EPCS.

      8. Nothing works because of broken ROMs content in the slave (and ONLY in the slave). Look at the previous post, I've described there how to detect those errors.

      9. Reload the slave .sof via JTAG. Or both master and slave. No changes, ROM still has errors.

      10. Reload ROMs via ISCME. No errors.

      I want to empasis the problem - .mif files used for ROM initialization in project don't get in ROMs intact. And this problem exists only for slave.

      • hareesh's avatar
        hareesh
        Icon for Frequent Contributor rankFrequent Contributor
        4 years ago

        hi

        can you please share your platform design and files.

        thanks.

  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    4 years ago

    hi @Vic3Dexe ,

    scope shot from oscilloscope is required so we know what happened in the trace DATA and DCLK. can you share that

    thanks,

    • Vic3Dexe's avatar
      Vic3Dexe
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      No problem as soon as someone share oscilloscope to me.

      Where exactly you need traces? AS_DCLK/AS_DATA or SOUTH_DCLK/SOUTH_DATA (after buffers)?

      I've cut traces and placed series resistors afters buffers (51R). Should I remove them before measurement?

      • hareesh's avatar
        hareesh
        Icon for Frequent Contributor rankFrequent Contributor
        4 years ago

        it's better to share at two points and one time measure with resistors and another time with out.

        on data line and clk line are you using 51R resistor only ?