Vic3Dexe
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Re: Cyclone III slave (PS) embedded memory errors
I think I've found the problem. There is a trace connected to pin 76 on the master and pin 99 on the slave. Trace is pulled up to 3.3V via 2.2k This **bleep** resistor was dead, and the trace was actually floating. I didn't use this pins before, so I can't reveal the resistor is dead. As I start to use it, all logic became a total mess. Something worked, something not. By elimination I found the culprit. I can't explain how this trace connected with loading errors (when FPGA not even in user mode), but the fact is - replacing resistor solved all problems, ROMs working now (though I don't use them anymore). Thanks to all, problem solved!Re: Cyclone III slave (PS) embedded memory errors
@hareesh wrote: @Vic3Dexe wrote: I've cut traces and placed series resistors afters buffers (51R) those resistors where are you connecting (data line or clk line or on both lines) if you see bellow attachment in schematic on clk and data lines using two different resistors in series. As I said in post 4: I've tried to remove buffers and change them to zero Ohm resistors - no changes. Then I've replaced 0R resistors to 51R ones - no changes. Then I've put buffers back, cut traces afters them (which are facing to the slave), and put 51R there in series. No changes. So now it's like that. Both resistors placed as close as possible to buffers. There is no point in resistors before buffers, as the master working ok.Re: Cyclone III slave (PS) embedded memory errors
1. MIF files were generated only once. I don't change them. They are constant. It's irrelevant how they are maked, because they don't change. 2. I have 2 projects in Quartus (13 sp1 web version) - one for master, and one for slave. 3. In both projects I've created "ROM 1-port" megafunctions (1 for master, and 2 of them for slave) and set according .mif files as init values. Like this: 4. Compiled (or fully recompiled) both projects, so the result is two .sof files. 5. Used convert programming file tool to create .pof file: 6. Used programmer to write EPCS: Here is the quartus log (one of the million attemp to get it to work). Verification also always passes (if enabled). Info (209060): Started Programmer operation at Tue Jun 21 17:23:18 2022 Info (209018): Device 1 silicon ID is 0x14 Info (209044): Erasing ASP configuration device(s) Info (209024): Programming device 1 Info (209018): Device 1 silicon ID is 0x14 Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Tue Jun 21 17:25:47 2022 7. Power up/reset the board. Both devices loads its content from EPCS. 8. Nothing works because of broken ROMs content in the slave (and ONLY in the slave). Look at the previous post, I've described there how to detect those errors. 9. Reload the slave .sof via JTAG. Or both master and slave. No changes, ROM still has errors. 10. Reload ROMs via ISCME. No errors. I want to empasis the problem - .mif files used for ROM initialization in project don't get in ROMs intact. And this problem exists only for slave.
