cyclone iii nios boot from epcs

Hi Happy420,

Could you tell us how is the epcs_controller.flash created ? Actually you don't have to do anything with the epcs_controller_boot_rom.flash, it's already included in the VHDL.

I just want to exclude any confusing between your code which you have to write in the epcs and the small rom bootloader.

Regards

Thanks, I think it's closer! The fpga logic is definitely being booted correctly from the epcs ( have it toggling an i/o), but the nios code doesn't execute at all ( a different i/o).

The reset vector in the sopc is pointing to the epcs controller peripheral (no offset), and the Nios IDE is setup to have everything run in external sram. If I power-on and allow the epcs to boot the fpga logic, and then I just download the nios code using the ide afterwards, then the nios program also works fine. So it seems it's only the nios portion (either flashed in the epcs or with the bootloader) that has the problem.

As a test for now, I am flashing both the fpga logic and the nios via the Nios IDE. The tool doesn't have any option to specifically specify the use of "epcs_controller_boot_rom.flash"... so I simply check the box to flash the software project and the FPGA configuration data (pointing to the sof file). During programming I see perform 2 flashes (each with checksum/verify/erase/programming):

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=0x04121800 --cable='U

SB-Blaster [USB-0]' --sidp=0x041220b8 --id=519100584 --timestamp=1322097713 "FpgaLogic.flash"

and

# Programming flash with the project

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=0x04121800 --cable='U

SB-Blaster [USB-0]' --sidp=0x041220b8 --id=519100584 --timestamp=1322097713 "ep

cs_controller.flash"

I get no errors when flashing, yet only the fpga logic works on power-on. What can I check for?

Hi Happy420,

In SOPC builder (or Qsys), you have added a "epcs_flash_controller" module. This module has a ROM memory in which the "epcs_controller_boot_rom.flash" is stored. This memory contains some code given by altera to load your nios program from the epcs to the processor RAM memory. You don't need to change anything on it. Just tell your processor to start from this memory with the processor's reset_vector set on the epcs_flash_controller.

To store your program in the epcs, you could try this method I use : http://www.alteraforum.com/forum/showpost.php?p=127299&postcount=2

For your problem with the nCS pin continuously toggling, It could be that you only have write the nios program in the epcs, but not the VHDL.

The second ligne creates a flash file with the elf file at an offset the size of the vhdl.flash file. So in your hex file, you have only the nios code beginning at a non zero address.

You could check if CONF_DONE pin rise or not.

Regards

Gotcha..

I have a little twist...

Trying to program a .pof on the epcs directly, so in quartus I open the Convert Programming File window. select the fpga sof file, and then add (nios) Hex data immediately after (absolute addressing)

However, the nios ide outputs an elf and strangely enough it also outputs a file called, "epcs_controller_boot_rom.flash".

So to generate a hex file that could be used as an input to make an epcs pof file...

if I do this:

nios2-elf-objcopy --input-target srec --output-target ihex input.elf output.hex

it produces a hex file that apparently exceeds the epcs capacity when added after the sof file.

if I do this:

nios2-elf-objcopy --input-target srec --output-target ihex epcs_controller_boot_rom.flash output.hex

Quartus complains that data in hex file overlaps between data blocks at address 1 and address 0.

However, if I do this:

1) sof2flash --verbose --compress --epcs --input=input.sof --output fpga.flash

2) elf2flash --verbose --epcs --after=fpga.flash --input=input.elf --output=app.flash

3) nios2-elf-objcopy --input-target srec --output-target ihex app.flash output.hex

Then it fits and I can program it, but at power-on, the nios does not appear to be running (no blinking led). Interestingly, the nCS on the epcs is continuously toggling. I would expect it to be active only during config/boot and then to stay high.

So long story short, how do you create a epcs .pof file that has the fpga image and nios code??

Correct !

In fact the FPGA Image is read byte after another so inside the EPCS some kind of actual adresspoint is set and incremented, after the last FPGA image byte, this pointer points to the first byte of the application software and the boot loader can fetch again one byte after another continuing the data stream.

So just ensure that your application is directly after the fpga image.

This means whenever you change your application, you need to assemble to complete EPCS image again.

You don't need to know the NIOS app's offset.

If you've placed the NIOS app right after FPGA image, then the EPCS bootloader will detect the FPGA image, calculate the size of the image, skip it and start executing the NIOS application.

That's why you have to set the reset vector to the offset 0x0000 of your EPCS Controller (that's where the bootloader is located).

More details can be found from the following Altera documents:

- Embedded Peripherals IP User Guide (the section "EPCS Serial Flash Controller Core")

- Application note 458 "Alternative Nios II Boot Methods"

Regards,

Jari

--- Quote Start ---

don't forgett to add the option --base=0x.... the startadr. of your epcs ip

inside sopcs builder you need to set the cpu reset vector to the epcs ip modul

--- Quote End ---

I'd like to give this a whirl.. basically boot the fpga and nios from epcs, and have the bootloader move everything to external sram.

However, I'm not sure about the reset vector in the sopc. Im using quartus/nios version 8.1, and you can set the epcs as the device to use for the reset vector, but shouldn't the offset be specified as the address of the epcs just AFTER the fpga image is stored? Because the base address of the epcs (i.e. offset 0) will contain the fpga config, no? If I do need to use the nios app offset, where do I find that?

Is there anything in the Nios Ide that needs to be specified, that after power on, or reset, the nios will jump (autoincrement) to the offset in the epcs memory to bootload, and copy the data to sram?

Thanks!

There is a bug the software template project "memory test" in nios 10.0.

Some variables refer to epcs_controller but Sopc builder name its variable epcs_flash_controller. I change all wrong names in the project and it works.

(verify in sytem.h, the name should be epcs_flash_controller).

Quartus II V9.0 SP2 and Cyclone III boots from EPCS.

One of my projects uses an EP3C40 set to boot from EPCS works fine after upgrading Quartus from 8.1 to 9.0 SP2. The projects had been regenerated and full compiled with 9.0Sp2

Quartus 8.1 is no longer installed so all tools run from 9.0sp2 and i see no issue with epcs boot.