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don't forgett to add the option --base=0x.... the startadr. of your epcs ip
inside sopcs builder you need to set the cpu reset vector to the epcs ip modul
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I'd like to give this a whirl.. basically boot the fpga and nios from epcs, and have the bootloader move everything to external sram.
However, I'm not sure about the reset vector in the sopc. Im using quartus/nios version 8.1, and you can set the epcs as the device to use for the reset vector, but shouldn't the offset be specified as the address of the epcs just AFTER the fpga image is stored? Because the base address of the epcs (i.e. offset 0) will contain the fpga config, no? If I do need to use the nios app offset, where do I find that?
Is there anything in the Nios Ide that needs to be specified, that after power on, or reset, the nios will jump (autoincrement) to the offset in the epcs memory to bootload, and copy the data to sram?
Thanks!
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