cyclone iii nios boot from epcs

if you want that the fpga image is loaded from epcs after power on the you must set the msel pins according to the datasheet of your fpga.

is your fpga image loaded from epcs but nios does not boot from epcs ?

did you store your application after the fpga image inside epcs device ?

converting the fpga image to be stored into epcs

bash -c "sof2flash --verbose --compress --epcs --input=fpga.sof --output=fpga.flash"

converting your application

bash -c "elf2flash --verbose --epcs --after=fpga.flash --input=app.elf --output=app.flash"

programming the fpga image

nios2-flash-programmer.exe --cable='USB-Blaster' --epcs fpga.flash

programming the application image

nios2-flash-programmer.exe --cable='USB-Blaster' --epcs app.flash --go

don't forgett to add the option --base=0x.... the startadr. of your epcs ip

inside sopcs builder you need to set the cpu reset vector to the epcs ip modul

if msel pins are set to boot from epcs then everything should work

Thank you MSchmitt.

My fpga is ep3c25q240c8 My msel pins is 010 My epcs64 power is 3.3v

fpga image is loaded from epcs after power on

quartus 9.0 no sp

This my Nios II IDE Flash Programmer

# !/bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.#

cd D:/FPGA/sopc_cy3/software/memtest_usb/Debug# Creating .flash file for the FPGA configuration

"$SOPC_KIT_NIOS2/bin/sof2flash" --epcs --input="D:/FPGA/sopc_cy3/chip_top.sof" -

-output="chip_top.flash"

Info: *******************************************************************

Info: Running Quartus II Convert_programming_file

Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=chip_

top.opt D:/FPGA/sopc_cy3/chip_top.sof chip_top.pof

Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings

Info: Peak virtual memory: 73 megabytes

Info: Processing ended: Wed Sep 02 16:08:47 2009

Info: Elapsed time: 00:00:04

Info: Total CPU time (on all processors): 00:00:04

Info: *******************************************************************

Info: Running Quartus II Convert_programming_file

Info: Command: quartus_cpf --no_banner --convert chip_top.pof chip_top.rpd

Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings

Info: Peak virtual memory: 70 megabytes

Info: Processing ended: Wed Sep 02 16:08:51 2009

Info: Elapsed time: 00:00:04

Info: Total CPU time (on all processors): 00:00:04# Programming flash with the FPGA configuration

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=0x0008a000 --sidp=0x0

0088030 --id=6395680 --timestamp=1251442455 --instance=0 "chip_top.flash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

Reading System ID at address 0x00088030: verified

: Checksumming existing contents

00000000 : Verifying existing contents

00010000 : Verifying existing contents

00020000 : Verifying existing contents

00030000 : Verifying existing contents

00000000 : Reading existing contents

00010000 : Reading existing contents

00020000 : Reading existing contents

00030000 : Reading existing contents

Checksummed/read 12kB in 0.2s

00000000 ( 0%): Erasing

00010000 (25%): Erasing

00020000 (50%): Erasing

00030000 (75%): Erasing

Erased 256kB in 2.3s (111.3kB/s)

00000000 ( 0%): Programming

00010000 (25%): Programming

00020000 (50%): Programming

00030000 (75%): Programming

Programmed 245KB +11KB in 5.6s (45.7KB/s)

Did not attempt to verify device contents

Leaving target processor paused# Creating .flash file for the project

"$SOPC_KIT_NIOS2/bin/elf2flash" --epcs --after="chip_top.flash" --input="memtest

_usb.elf" --output="epcs_controller.flash"# Programming flash with the project

"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --epcs --base=0x0008a000 --sidp=0x0

0088030 --id=6395680 --timestamp=1251442455 --instance=0 "epcs_controller.flash"

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Resetting and pausing target processor: OK

Reading System ID at address 0x00088030: verified

: Checksumming existing contents

00030000 : Verifying existing contents

00040000 : Verifying existing contents

00050000 : Verifying existing contents

00030000 : Reading existing contents

00040000 : Reading existing contents

00050000 : Reading existing contents

Checksummed/read 110kB in 2.6s

00030000 ( 0%): Erasing

00040000 (33%): Erasing

00050000 (66%): Erasing

Erased 192kB in 1.8s (106.6kB/s)

00030000 ( 0%): Programming

00040000 (33%): Programming

00050000 (66%): Programming

Programmed 83KB +109KB in 4.0s (48.0KB/s)

Did not attempt to verify device contents

Leaving target processor paused

okay thats it, you use quartus 9.0 without sp2

can't tell you right out of my head what was the exact bug, but there is a bug with this quartus version and epcs stuff.

somebody mentioned at niosforum that mysupport said that this bug won't be fixed in sp1 but should be in sp2 and as long as there is no fix, users should unpack some files from quartus 8.1

unfortunately nobody said it is fixed in sp2, but i would install sp2 and give it a try.

sorry i do not use quartus 9.0 due to this bug until somebody says it is solved.

maybe you ?

solution id: rd06022009_270

last modified: Jul 10, 2009

product category: Embedded Processors

product area: Hardware Development

product sub-area: Flash Programming

problem

why does my cyclone iii nios ii system not boot up from an epcs device when i program the epcs with flash programmer ver.9.0?

solution

Nios® II embedded processor executable code is not correctly programmed on an EPCS device with version 9.0 and 9.0sp1 Nios II Flash Programmer tool chain.

Version 9.0 and 9.0sp1 contain a bug in the tool chain. To solve this problem, contact Altera® technical support via mysupport (http://mysupport.altera.com/) to request the Nios II EDS 1.01 patch.

This problem will be fixed by Nios II EDS version 9.0sp2 .

but i use quartus 7.1 is same .

other possability :

The workaround:

replace 90\nios2eds\bin\sof2flash.jar with 81\nios2eds\bin\sof2flash.jar

Quartus II V9.0 SP2 and Cyclone III boots from EPCS.

One of my projects uses an EP3C40 set to boot from EPCS works fine after upgrading Quartus from 8.1 to 9.0 SP2. The projects had been regenerated and full compiled with 9.0Sp2

Quartus 8.1 is no longer installed so all tools run from 9.0sp2 and i see no issue with epcs boot.

There is a bug the software template project "memory test" in nios 10.0.

Some variables refer to epcs_controller but Sopc builder name its variable epcs_flash_controller. I change all wrong names in the project and it works.

(verify in sytem.h, the name should be epcs_flash_controller).

--- Quote Start ---

don't forgett to add the option --base=0x.... the startadr. of your epcs ip

inside sopcs builder you need to set the cpu reset vector to the epcs ip modul

--- Quote End ---

I'd like to give this a whirl.. basically boot the fpga and nios from epcs, and have the bootloader move everything to external sram.

However, I'm not sure about the reset vector in the sopc. Im using quartus/nios version 8.1, and you can set the epcs as the device to use for the reset vector, but shouldn't the offset be specified as the address of the epcs just AFTER the fpga image is stored? Because the base address of the epcs (i.e. offset 0) will contain the fpga config, no? If I do need to use the nios app offset, where do I find that?

Is there anything in the Nios Ide that needs to be specified, that after power on, or reset, the nios will jump (autoincrement) to the offset in the epcs memory to bootload, and copy the data to sram?

Thanks!