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Honored ContributorCyclone III configuration corrupts image
All,
We have 30 boards with a single EP3c25 wired for JTAG and AS configuration, as per the handbook. Several pairs of eyes have peered at the schematic and the boards and everything looks like it should. But, on most of the boards, configuration with USBBlaster results no errors but a corrupt FPGA image in the chip. Multiple tries will usually result in one good configuration that allows us to program the EPCS. Once that is done the boards work reliably. Except that they are still as difficult to configure through JTAG as ever. The problem varies from board to board. Some are good, some are not so good and others are completely useless. Most of the boards are flaky to useless. All the voltages look good. JTAG signals look clean. The programming software generates no errors. CONFIG_DONE goes high even though the image is bad. (We can tell by LEDs on the board if the image took or not.) We've made Altera and Cyclone III boards before and have not had these kinds of problems. What could possibly be causing this?23 Replies
Altera_Forum--- Quote Start --- It turns out that it's a power problem. --- Quote End --- I'm glad you solved it. What was the power problem? (So others can avoid making it) Cheers, Dave- Altera_Forum
At this point, nobody is really sure what the problem is. It's just that when we bypass the 5v regulator and feed in 5v from an external source, it goes from about 90% failure rate to 90% success rate. Don't know why it's glitching, still working on it.
- Altera_Forum--- Quote Start --- At this point, nobody is really sure what the problem is. It's just that when we bypass the 5v regulator and feed in 5v from an external source, it goes from about 90% failure rate to 90% success rate. Don't know why it's glitching, still working on it. --- Quote End --- Sounds like progress, anyway :) Let us know what you find. Cheers, Dave
- Altera_Forum
Two turns of the board later, we still have a problem.
I enabled CRC and see a CRC error on the bad downloads, so the image is indeed corrupt. One thing we discoverd by accident is that if we connect 3.3v to the 2.5 rail, the board works like a champ. We've tried this on several boards and not only do the program but, in all ways, seem just fine. Why should this work? What harm might we be doing to the chip? Anybody? - Altera_Forum--- Quote Start --- Why should this work? What harm might we be doing to the chip? Anybody? --- Quote End --- Its a bit hard to comment without seeing the design. Can you post the schematics? Have you probed the power rails and looked at their power-on timing and sequence relative to each other? Have you checked the errata? Have you looked at the clock signals on the board, are there glitches/reflections on anything, eg., the JTAG clock, DCLK, the core clock. If voltages and clocks are all within spec, then you should not have any issues. Where did you buy the devices? Are you sure the devices have not been pulled from boards, re-packaged, and re-sold? Try a part purchased through another distributor. Cheers, Dave
- Altera_Forum
I'm just trying to understand here: How could power-up conditions effect JTAG programming, many seconds after power on, but not effect programming via EPCS?
The relevant part of the schematic is attached. - Altera_Forum--- Quote Start --- I'm just trying to understand here: How could power-up conditions effect JTAG programming, many seconds after power on, but not effect programming via EPCS? --- Quote End --- If it was only happening on one board, you might be able to hypothesize that if say nCE was not connected, that it was 'low' enough at power on for EPCS configuration, but then floated high, so that JTAG configuration would not work. I'll look at the schematic page. Cheers, Dave
- Altera_Forum
What do you currently have on nCE? Why not tied it to ground via 0-Ohms?
Are you creating your configuration file to enable INIT_DONE? Otherwise your LED will not light up, and you might just think that your configuration failed. Cheers, Dave - Altera_Forum
nCE was reworked from 300 to 10K, from "Cyclone II device family pin connection guidelines PCG-01003-1.1" - and using 10K actually makes it work a little better.
INIT_DONE is enabled. So is CRC. (note what I said earlier) Interestingly, INIT_DONE doesn't seem to work when programming via JTAG, but once the image is burned into EPCS, it does. How do I know the image is corrupt? 1. The CRC light is on. 2. LEDs that are supposed to be off are on. 3. We can't talk to the NIOS inside the chip. So, the issue of the day is: what kind of problem would go away when we raise the voltage from 2.5 to 3.3? - Altera_Forum--- Quote Start --- INIT_DONE doesn't seem to work when programming via JTAG, but once the image is burned into EPCS, it does. --- Quote End --- I assume that you're not telling the tool you're using an external CLKUSR? (Just a suggestion) --- Quote Start --- So, the issue of the day is: what kind of problem would go away when we raise the voltage from 2.5 to 3.3? --- Quote End --- The only voltages you have at 2.5V are the VCCA/VCCD voltages right? Do these voltages even need to be powered for the device to exit power-on-reset? (Check the handbook). Try not powering them at all and see what happens. Cheers, Dave
