Honored ContributorHello. I am implementing an arbitrary waveform generator using a EP3C16 device to drive a DAC using a 600 MHz LVDS Interface. Should I clock the FPGA with a 600 MHz oscillator directly or should I use a low frequency crystal (running at tens of Mhz) and multiply the clock frequency internally using one of the device's PLL?
Thank you
Honored ContributorNaturally a slower board clk is better. But can you achieve 600MHz speed(fmax) inside fpga?
Honored ContributorI would suggest using an internal PLL to do the 600MHz clock generation to ease routing issues external to the FPGA.
That said 600MHz is quite a challenging speed to tun your FPGA logic at.Honored ContributorWell, here is some more about the project. I am going to use external SRAM memory running at 200 MHz and implement a multiplexer inside the FPGA that receives data at 200MHz/36 bits and sends data to the Cyclone III LVDS dedicated outputs at 600 MHz/12bits. According to the device's datasheet a device with a speed grade of 8 (like the one I use) is able to send data through its dedicated LVDS pins with a maximum speed of 640 MHz. Of course that's only in theory.
Honored ContributorFor output lvds pins I don't doubt the 640MHz speed but we are talking about your fpga logic at 600MHz !! very hard to achieve.
Honored ContributorJust a thought, I wonder if you can exploit serdes for this application. I mean with a serialisation factor of 36:12 can you serialise out each 36 bits onto 12 channels. The DAC will then read it direct on 600MHz(without deserialser of course).
A serialisation factor of 3:1 means every 3 bits (of 36) will be passed serially to one channel. Thus you need some bit-mapping to get it work: ch1 to serialise bit0, bit12, bit 24 ch2 to seriliase bit1, bit13, bit 25 ...etc note the paradox here: you serialise data to read it as parallelHonored ContributorAs already mentioned, Cyclone III LEs can't handle 600 MHz. The maximum clock tree speed in C6 speed grade (which is obviously the absolute maximum for any internal clocked logic as well) is 500 MHz.
Cyclone FPGA families achieve higher LVDS speeds by DDIO cells (Double edge clocked IO cells). They are also the central element in Cyclone soft SERDES blocks. With DDIO, you can realize 600 MHz data rate. Because DDIO is operating as a 2:1 multiplexer, odd SERDES factors as 3:1 involves bulky additional logic. Actually I'm not sure, if 3:1 will work at all with 600 MHz. It would be much easier to change your design e.g. to a 4:1 factor.
