Cyclone III Clock and PLL issues

As already mentioned, Cyclone III LEs can't handle 600 MHz. The maximum clock tree speed in C6 speed grade (which is obviously the absolute maximum for any internal clocked logic as well) is 500 MHz.

Cyclone FPGA families achieve higher LVDS speeds by DDIO cells (Double edge clocked IO cells). They are also the central element in Cyclone soft SERDES blocks. With DDIO, you can realize 600 MHz data rate. Because DDIO is operating as a 2:1 multiplexer, odd SERDES factors as 3:1 involves bulky additional logic. Actually I'm not sure, if 3:1 will work at all with 600 MHz. It would be much easier to change your design e.g. to a 4:1 factor.