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Altera_Forum
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16 years ago

Cyclone III Clock and PLL issues

Hello. I am implementing an arbitrary waveform generator using a EP3C16 device to drive a DAC using a 600 MHz LVDS Interface. Should I clock the FPGA with a 600 MHz oscillator directly or should I us...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Well, here is some more about the project. I am going to use external SRAM memory running at 200 MHz and implement a multiplexer inside the FPGA that receives data at 200MHz/36 bits and sends data to the Cyclone III LVDS dedicated outputs at 600 MHz/12bits. According to the device's datasheet a device with a speed grade of 8 (like the one I use) is able to send data through its dedicated LVDS pins with a maximum speed of 640 MHz. Of course that's only in theory.