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Altera_Forum's avatar
Altera_Forum
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16 years ago

Cyclone III Clock and PLL issues

Hello. I am implementing an arbitrary waveform generator using a EP3C16 device to drive a DAC using a 600 MHz LVDS Interface. Should I clock the FPGA with a 600 MHz oscillator directly or should I us...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I would suggest using an internal PLL to do the 600MHz clock generation to ease routing issues external to the FPGA.

That said 600MHz is quite a challenging speed to tun your FPGA logic at.