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Altera_Forum
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16 years ago

Cyclone III Clock and PLL issues

Hello. I am implementing an arbitrary waveform generator using a EP3C16 device to drive a DAC using a 600 MHz LVDS Interface. Should I clock the FPGA with a 600 MHz oscillator directly or should I us...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Just a thought, I wonder if you can exploit serdes for this application. I mean with a serialisation factor of 36:12 can you serialise out each 36 bits onto 12 channels. The DAC will then read it direct on 600MHz(without deserialser of course).

A serialisation factor of 3:1 means every 3 bits (of 36) will be passed serially to one channel. Thus you need some bit-mapping to get it work:

ch1 to serialise bit0, bit12, bit 24

ch2 to seriliase bit1, bit13, bit 25

...etc

note the paradox here: you serialise data to read it as parallel