cyclone iii altlvds_tx and altlvds_rx?

i want to use altlvds_tx to transmit 16 bit data,so i set 2 channels,the deserialization factor is 8, ues externel pll. the data rate is 160Mpbs.

so the pll has two output clocks,c0 and c1, c0 is 80Mhz and c1 is 20Mhz.

but i don't konw how to set the phase.

then i link c0 to the tx_inclock,c1 to the syncclock,the altlvds_tx out put only have tx_out pin,so where is the clock output?

if i want use altlvds_rx to receive, i set 2 channels,the deserialization factor is 8, ues externel pll,so it has port:rx_in,rx_inclock,and rx_out.so what is the frequency of the rx_inclock,i don't have the tx_outclock?

so where is the rx_outclock? i am confuse with this problems.

appreciate for all helps.