Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Cyclone 4 deserialization, banks, pll

Dear Gurus; I have 1 Cyclone IV GX EP4CGX150(DF27C7) This Cyclone IV is connected to 6 x Cyclone III (C40F484) All of these 6 Cyclone IIIs will send 4 bit LVDS serialized input data ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I guess, the accompanying clock is a frame (slow) clock. Then each receiver needs a separate PLL to generate a bit clock for the respective channel In other words, you can't implement 6 receivers in a single Cyclone IV.

If some prerequisites are met (>600 MBPS bit rate, coding with maximum run length, embedded sync patterns), GX receivers may be also utilized.