Cyclone 2 + MLVDS transciever = PLL problem?

Hi

We are using a NIOS2 processor and some VHDL code inside a Cyclone 2 240 pin package. Connected to the FPGA are 2 SRAM chips, EPCS16 and a couple of MLVDS transceivers, namely MLVD080 and MLVD205 from TI.

This is the problem we are experiencing on our boards:

If the system is configured to run directly from the input clock 32.768MHz on pin 92 then the system runs fine (NIOS and VHDL).

But if we use the PLL with the VDDD and VDDA on pins 121 and 123 respectively the PLL loses lock with the frequency of the accesses to the MLVD080. The power supply for the PLL is as recommended by Altera (VDDA is filtered with a ferrite bead and a bank of capacitors from 2u2 down to 10nF, same for VDDD without the ferrite bead). The MLVD is blocked on its power supply with 100nF capacitors, also we tried adding bigger capacitors, 22uF, with no result. VDDD was also filtered the same way as VDDA, no effect. The board has 4 layers, with a power plane covering the whole board with cutouts for the 1.2V supply rail and a ground plane. Surrounding the PLL are data lines that go to and from the MLVD.

We are contempt with the design running without the PLL but we would like to know what is behind this problem, since it may arise in the future the need for the PLL.

Thank you in advance. :)