Cyclone 10 LVDS SERDES Receiver refclk for multiple I/O banks

Question

Dear All,we are using Cyclone 10 (10CX105YF780E6G) and we have to implement an LVDS Receiver for 33 rx_in channels with only one rx_inclk at a data rate of 900Mbps. So, we need at least 2 I/O banks and 2 LVDS SERDES instances.
How can we use the same rx_inclk for several LVDS SERDES instances with their I/O PLLs?Can we use the Global clock network for the reference clock to the I/O PLLs?
Best regards,Bohris

amint_intel · Answer

Hello Bohris,

May I know which version of Quartus are your team using for this design?

Thanks.

bohris · Answer

We are using Quartus Prime Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition.

amint_intel · Answer

Hello,

I think 900 MHz desired inclock frequency is out of range.

Thanks.

amint_intel · Answer

Hello Bohris,

You can try do that on Pin Assignment tab.

Thanks.

bohris · Answer

The PLL inclock frequency of our design is 450MHz for a data rate of 900Mbps.
Reducing the LVDS Receiver SERDES to 8 rx_in channels with the PLL reference clock on the same bank as the data channels, the compilation is successful.
With more than 8 rx_in channels we want to use the PLL reference clock from another bank. Is this possible?

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Cyclone 10 LVDS SERDES Receiver refclk for multiple I/O banks

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