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Bohris's avatar
Bohris
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5 years ago

Cyclone 10 LVDS SERDES Receiver refclk for multiple I/O banks

Dear All, we are using Cyclone 10 (10CX105YF780E6G) and we have to implement an LVDS Receiver for 33 rx_in channels with only one rx_inclk at a data rate of 900Mbps. So, we need at least 2 I/O b...
AminT_Intel's avatar
AminT_Intel
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5 years ago

Hello,

I think 900 MHz desired inclock frequency is out of range.

Thanks.

  • Bohris's avatar
    Bohris
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    5 years ago

    The PLL inclock frequency of our design is 450MHz for a data rate of 900Mbps.
    Reducing the LVDS Receiver SERDES to 8 rx_in channels with the PLL reference clock on the same bank as the data channels, the compilation is successful.
    With more than 8 rx_in channels we want to use the PLL reference clock from another bank. Is this possible?

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hello Bohris,

      I am sorry to tell you that that is not possible because IOs on each banks work independently. I hope you can work your design around this constraints.

      Thanks.