Annu
New Contributor
New ContributorCyclone 10 LP True DPRAM IP
In Cyclone 10 LP device, TRUE DPRAM IP with single clock is not writing on the odd addresses why is it so
Forum Discussion
AnnuNew Contributor
New ContributorMy RAM is accessed by a Processor where processor is trying to write byte by byte But My RAM is word based. If we try writing byte by byte, does it corrupts the RAM
ShengN_altera
Super Contributor
Super ContributorYes, a word-based RAM expects aligned word writes, not arbitrary byte writes — unless byte enable is properly handled. You have to properly use the byte enable like for example (2'b11 for 16 bits)
Take an example:
Assume:
- RAM width = 16-bit (2 bytes)
- Addressing = word-based
Address mapping:
| Processor addr | RAM addr | Byte lane |
|---|---|---|
| 0 | word 0 | low byte |
| 1 | word 0 | high byte |
| 2 | word 1 | low byte |
| 3 | word 1 | high byte |
If your design:
- Always writes full word
- OR only enables byteena[0] (
If byte enable is missing or wrong)
Then:
| Address | Result |
|---|---|
| Even (0,2,...) | writes lower byte |
| Odd (1,3,...) | upper byte ignored |
You may check the waveform for byteenable from this doc https://cdrdv2-public.intel.com/654378/ug_ram.pdf (page 39)
