New Contributor
New ContributorThanks for answering ! I'm already sure that my QSF pin assignments is not an issue because I will not use the IO pins lost in 10CL006 U256 (These pins are connected to GND 1.2V or 2.5V with 10CL025) : I put all these pins in QSF as inputs with no weak pull-up.
I need "a confirmation that the 10CL006 FPGA will not have an abnormal behaviour with power voltage on these inputs located in the forbidden zone (between Vil and Vih) : as no FlipFlop (and consequently no CLK rising edge) are connected to these inputs, it should be OK ? No metastability or something else wrong ?"
Occasional ContributorHi Zian,
Please refer to the pin connection guideline for the specific pins like pll/clock pins.
https://www.intel.com/content/www/us/en/docs/programmable/683137/current/clock-and-pll-pins.html
If it is a GPIO pins, it would be OK for leaving it without any pullup or pulldown.
But in general, we suggest to set it as tristate for the safety of circuit.
Thanks,
Ethan
